1. Field of the Invention
The present invention is generally directed toward transferring data of multiple voltage levels between data busses. More specifically, the invention relates to transferring data between devices on a first data bus and a second data bus where the data buses use different signal voltage levels and where the second bus utilizes multiplexing structures to apply data to each of multiple devices coupled thereto.
2. Discussion of Related Art
Many circuit components transfer data between one another. Typically, the circuit components transfer the data through a data bus when parallel communications are desired. Some circuit components operate on voltages that differ from operating voltages of the other components. To ensure the voltage tolerances of each component are not breached, the components are often grouped according to operating voltage levels. Each group of components is connected to a data bus that serves a particular operating voltage level for a specific group of components. For example, a group of components that operates on 3.3 Volts (V) is connected to a 3.3V tolerant data bus, and a group of components that operates on 5V is connected to a 5V tolerant data bus.
In a circuit configuration, many of the components within each group must communicate to components within other groups. Since the voltages between the groups of the components may differ, a bi-directional voltage level shifter is typically employed to translate the voltage level of the data on one data bus to another voltage level for another data bus. As in the previous example, data being transferred from the 5V tolerant data bus to the 3.3V tolerant data bus would be translated, or “stepped down”, to 3.3V by the bi-directional voltage level shifter that is connected to each of the data buses.
While the bi-directional voltage level shifter serves the function of translating voltage levels between two data buses, a problem arises as circuits attempt to add more components to increase functionality. For example, a 3.3V bus master device may need to communicate to a 5V Non Volatile Synchronous Random Access Memory (NVSRAM) through the bi-directional voltage level shifter. To control the NVSRAM, the bus master device must use address-decode logic to access addresses of the NVSRAM. Often the address-decode logic is integrated with the voltage level shifter in a custom logic circuit. The address-decode logic increases circuit size and pin count of such a custom circuit. The increase in pin counts due to the addition of components increases costs and decreases reliability as more pins provide potential for additional faults and may require the use of larger, more costly custom programmable integrated circuits.
One example of an additional component that may be coupled to the second bus is a diagnostic display such as a bank of Light Emitting Diodes (LED) used as indicators. Such LEDs are often used to add functionality to a circuit by allowing a user to view certain operative characteristics of the circuit. For example, the LEDs may be used to indicate a likely failure mode for service technicians or may be used to indicate status of the associated device. When the LEDs are added to the circuit and connected such that the LEDs are controlled by a bus master device, an additional latch device is often used to transfer control data from the bus master device to the LEDs and to latch the transferred data for continued display on the LEDs. The latch device holds the control data such that the LEDs remain illuminated for as long as necessary. The additional latch device also increases circuit size and pin count, further increasing costs and decreasing reliability. Furthermore, the LEDs consume power inefficiently and increase operating costs of the circuit.
As evident from the above discussion, a need exists for improved structures and methods for increasing functionality of such a circuit while decreasing pin counts and improving circuit reliability.